1. Field
Aspects of the present disclosure relate to semiconductor devices, and more particularly to a high-k/conductive gate embedded flash multiple time programmable (MTP) non-volatile memory.
2. Background
In semiconductor devices, memory is often used to configure the functions of logic blocks and the routing of interconnections between devices and circuits. For power and size considerations, programmable non-volatile memories (NVM), (e.g., multiple time programmable (MTP) non-volatile memories), may be used to allow for customization of circuit operation.
NVM MTP memories may be fabricated from complementary metal-oxide-semiconductor (CMOS) circuits using field-effect transistor (FET) components. Recently, different structures for the transistors in CMOS have been introduced, where the transistor is a “fin” shaped (3D) structure. These structures are often referred to as “FinFET” structures.
There are some associated problems with using FinFETs in CMOS non-volatile memory applications. FinFETs may use additional voltage to couple a floating gate structure to the fin. Because the upper portion of the fin area (the width of the fin times the length) is often small, an additional program (write) voltage is used to couple the gates together in series, which may negate the power savings realized in CMOS circuitry. Further, MOS diodes used for coupling, (e.g., for the floating gate of a memory cell), only bias in a positive direction. Positive-only biasing makes it difficult for negative voltages to be used to program (“write to”) or erase to/from a floating gate memory cell.